1. Field of the Invention
The present invention relates to a semiconductor memory device constituting the memory cell of a CMOS static RAM.
2. Description of Related Art
FIG. 9 is a layout configuration diagram showing a conventional semiconductor memory device.
Referring to FIG. 9, reference numeral 1 denotes an one-bit SRAM, reference numerals N1, N2, N3, and N4 denote NMOS transistors formed in a P well region, and reference numerals P1 and P2 denote PMOS transistors formed in a N well region. The NMOS transistor N1 and PMOS transistor P1 make up a first inverter, and the NMOS transistor N2 and PMOS transistor P2 make up a second inverter.
Reference numeral a1 denotes a first metal wiring a1 which connects the drain of NMOS transistor N1 with that of PMOS transistor P1, reference numeral a2 denotes a second metal wiring which connects the output terminal of the first inverter with the input terminal of the second inverter, and the first metal wiring a1 and second metal wiring a2 make up a memory node. Reference numeral b1 denotes a first metal wiring b1 which connects the drain of NMOS transistor N2 with that of PMOS transistor P2, reference numeral b2 denotes a second metal wiring which connects the output terminal of the second inverter with the input terminal of the first inverter, and the first metal wiring b1 and second metal wiring b2 make up a memory node.
Reference numeral C denotes a diffusion contact hole, reference numeral GC denotes a gate contact hole, reference numeral VDD denotes the power supply potential of a P+ diffused region formed in the N well region, reference numeral GND denotes the ground potential of a N+ diffused region formed in the P well region, reference numeral WL1 denotes a word line connected with the gate of the NMOS transistor N3, reference numeral WL2 denotes a word line connected with the gate of the NMOS transistor N4, reference numeral BL1 denotes a bit line connected with the drain of the NMOS transistor N3, and reference numeral BL2 denotes a bit line connected with the drain of the NMOS transistor N4.
The operation will next be described.
When parts are laid out as shown in FIG. 9, a SRAM can be formed into the circuit configuration shown in FIG. 2.
When a semiconductor memory device as shown in FIG. 9 is formed, for instance, the NMOS transistors N1, N2, N3, and N4, the PMOS transistors P1 and P2, the first metal wirings a1 and b1, and the word lines WL1 and WL2 are formed in the first layer. The second metal wirings b1 and b2 are formed in the second layer, and the bit lines BL1 and BL2 are formed in the third layer.
Such an arrangement of the conventional semiconductor memory device as mentioned above contributes to enhancement of the integration degree of the SRAM. However, this arrangement requires the second metal wirings a2 and b2 to be wired in a layer different from the first metal wirings a1 and b1. For this reason, in proportion to the increase in the number of the wiring layers, manufacturing processes increase. As a result, this brings about long manufacturing terms and high manufacturing costs.
In addition to the above-described prior art, JP-A-28401/2001 discloses a technology in which the second metal wirings a2 and b2 are wired in the same layer as the first metal wirings a1 and b1 by dividing the P well region. However, in this case, because one word line is shared, the word line must be wired in a different layer.